Digital integrated circuits such as microprocessors have output and input/output signal lines for such functions as address, data, and control signals. Each output or input/output signal line has an output buffer associated with it which is used to drive a corresponding signal to an appropriate logic level. In general, it is desirable for output buffers to be fast, to have low switching noise, to be compact, and to have low power consumption.
Each integrated circuit output, input, or input/output signal line is typically routed on a printed circuit board to other integrated circuit components. The metal conductors which route the signals between the integrated circuits can be modeled as capacitors which must be charged or discharged to the appropriate logic levels. Because the capacitive loading of these signal lines is relatively large compared to the loading within the integrated circuit, buffer switching accounts for a significant portion of the energy consumption of the integrated circuit. As integrated circuit geometries continue to shrink, internal loading also decreases but board-level loading stays relatively constant. Thus, the portion of integrated circuit energy consumption due to external loading as a share of overall energy consumption increases. While many output buffer circuit design techniques have already addressed the speed and switching noise problems, new techniques to reduce power consumption are needed.
Much energy is consumed in the integrated circuit because the output buffers continually charge and discharge the large board capacitance. When an output buffer drives the signal line to a logic high voltage, charge is transferred from the more positive power supply voltage terminal, designated "V.sub.DD ", to the board capacitor. When the output buffer next drives the signal line to a logic low voltage, the charge stored in the board capacitor is discharged to the more negative power supply voltage terminal, designated "V.sub.SS ", through the output buffer. Thus, the charge on the external capacitor is essentially "wasted".
Two circuit design techniques have attempted to overcome the problem of wasted charge. The first technique is known as the adiabatic computing technique. Adiabatic computing oscillates V.sub.DD between its normal voltage and a voltage close to ground. This technique reduces energy consumption by switching the state when V.sub.DD is at the low potential, thus minimizing the charge dumped to ground. However, this technique is difficult to implement. It requires an inductor-capacitor circuit to drive the V.sub.DD node, which in non-ideal circuits also includes parasitic resistance which undesirably damps the signal. The buffer circuit is also slow since the frequency of oscillation needs to be low.
The second technique is known as the switched capacitor technique. According to this technique, large on-chip capacitors ramp the output up and down slowly in a charge-coupling manner. However, the capacitors cannot be implemented compactly and the output buffer requires a large amount of integrated circuit area. It is also normally slow because several capacitors need to be switched to obtain a large power savings.
Thus, known charge-conserving output buffer schemes create other problems that make their use undesirable. What is needed is an integrated circuit output buffer design to reduce energy consumption which is relatively fast and compact. These needs are met by the integrated circuit of the present invention, whose features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.